Texas Instruments has qualified its 65-nm process technology only eight months after delivering first samples of a wireless device and is moving to volume manufacturing.

TI first disclosed details around its advanced 65-nm CMOS process in early 2004, and announced sampling of the wireless digital baseband processor in March 2005. The process technology doubles transistor density over the company’s 90nm process. TI’s technology significantly reduces leakage power from idle transistors while simultaneously integrating hundreds of millions of transistors that support both analog and digital functions in System on Chip (SoC) configurations.

Today’s advanced multimedia and high-end digital consumer electronics have increased processing demands and the focus on low power semiconductor technology development. To address the challenge, TI has implemented its SmartReflex^TM power and performance management technologies in its 65-nm platform in order to offer a combination of intelligent and adaptive silicon, circuit design and software designed to solve power and performance management challenges at smaller process nodes.

By closely monitoring circuit speed, SmartReflex technologies can dynamically adjust voltages to meet exact performance requirements without sacrificing overall system performance. As a result, minimum power is used for each operating frequency, extending battery life and reducing the amount of heat produced by the device.

Other techniques at 65-nm reduce power consumed by transistors when they are idle, including times when mobile phones are in standby mode waiting to receive calls. These innovations include back-biasing of SRAM memory blocks and retention flip-flop circuitry that allows voltages to drop extremely low without requiring a rewrite of logic or memory content. Together, these SmartReflex advancements can deliver up to a 1000 times reduction in power leakage.

The 65-nm process includes up to 11 layers of copper interconnect integrated with a low k dielectric, OSG, with a k of 2.8 - 2.9. Other improvements include an induced strain on the transistor channel during chip processing to increase electron and hole mobility; nickel silicide to lower both gate and source / drain resistance, and ultra-shallow source / drain junctions.