Samsung has developed the first all-DRAM stacked memory package using ‘through silicon via’ (TSV) technology, which will result in memory packages that are faster, smaller and consume less power.

The new wafer-level-processed stacked package (WSP) consists of four 512 Mb DDR2 (second generation, double data rate) DRAM (dynamic random access memory) chips that offer a combined 2 Gb of high density memory. Using the TSV-processed 2Gb DRAMs, Samsung can create a 4 GB DIMM (dual in-line memory module) based on WSP technology for the first time. The new technology reduces the overall package size and permits the chips to operate faster and use less power.

Samsung’s WSP technology forms laser-cut micron-sized holes that penetrate the silicon vertically to connect the memory circuits directly with a copper (Cu) filling, eliminating the need for gaps of extra space and wires protruding beyond the sides of the dies. These advantages permit Samsung’s WSP to offer a significantly smaller footprint and thinner package. Inside the new WSP, the TSV is housed within an aluminum (Al) pad to escape the performance-slow-down effect caused by the redistribution layer. Due to the complexity of DRAM stacking, this represented a much more difficult engineering feat than that accomplished with the first WSP, announced last year involving NAND flash dies.

Samsung’s WSP technology resolves the concern that MCPs (multi-chip packages) with high-speed memory chips with speed of 1.6Gb/ps next generation DRAM, would suffer from performance limitations when connected using current technologies.

As the back side of the wafer is ground away to make a thinner stack of multiple dies, the wafer has had a tendency to curve, creating physical distortion in the die. To overcome this concern in designing low-profile, high-density MCPs containing DRAM circuitry, Samsung’s wafer-thinning technology has been applied to improve the thin-die-cutting process.

“The innovative TSV-based MCP stacking technology offers next-generation packaging solution that will accommodate the ever-growing demand for smaller-sized, high-speed, high-density memory,” said Tae-Gyeong Chung, vice president, Interconnect Technology Development Team, Memory Division, Samsung Electronics. “In addition, the performance advancements achieved by our WSP technology can be utilized in many diverse combinations of semiconductor packaging, such as system-in-package solutions that combine logic with memory.