Toshiba Corporation have developed FeRAM - a Ferroelectric Random Access Memory and MRAM - a Magnetoresistive Random Access Memory, the last one in cooperation with NEC Corporation.

FeRAM combines the fast operating characteristics of DRAM and SRAM with flash memory’s ability to retain data while powered off, characteristics that continue to attract semiconductor industry attention.

The new chip takes FeRAM storage to the 64-megabit level employs a new wiring design in which neighboring wirings operate in sequence; one is off when the other is on. Its bandwidth (read/write speed) is up to 200-megabytes a second, world record for FeRAM. Fabricated with 130-nanometer CMOS process technology, with a cell size of 0.7191 um2, the 64-megabit FeRAM is based on Toshiba’s chainFeRAMTM architecture, which reduces memory cell size. It also integrates optimized circuitry designed to reduce the circuit area and squelch noise during read operation. Write data reliability is enhanced by ECC, an error checking and correcting circuit that detects and corrects write data errors. The new FeRAM also adopts a new control method that uses pseudo writing processing during error correction and that carries our write and error operations in parallel. This approach minimizes increases in write processing time resulting from error correction operation, cutting it to approximately 15% instead of approximately 30%.

Toshiba declared it will continue the research in FeRAM field, aiming for eventually use in a wide range of applications, including high-performance mobile digital equipment and computers.

The new MRAM achieves a 16-megabit density and a read and write speed of 200-megabytes a second, and also secures low voltage operation of 1.8Vthe ideal voltage for mobile digital products. A major challenge of MRAM development to date has been the acceleration of read speeds: the current drive circuit used to generate the magnetic field for writing degrades read operation from memory cells. The new MRAM has an improved circuit design that divides the current paths for reading and writing, realizing a faster read speed. It also reduces equivalent resistance in wiring by approximately 38% by forking the write current. These innovations together achieve a read and write speed of 200-megabytes a second and a cycle time of 34 nanoseconds â€â€? both the world’s best performance for MRAM.

Alongside advances in performance, the new MRAM achieves advances in chip size. Toshiba and NEC have introduced the above mentioned technologies and optimized overall circuit design, achieving a chip that, at 78.7mm2, is approximately 30% smaller than its equivalent without the new circuit design.

MRAM is expected to be a next-generation non-volatile memory that retains data when powered off and that achieves fast random access speeds and unlimited endurance in operation.